A cache is a relatively small, high speed memory that is used to increase the speed of a data processing system. The access time of the cache is close to the central processing unit (CPU) logic propagation delay. The cache stores frequently used instructions or data to reduce the number of accesses between the CPU and a relatively slower main memory, thus improving system performance.
A cache TAG comparator is frequently used to increase the performance of the cache. The cache TAG comparator receives an address that is provided by the processor and determines if the requested instructions or data are present in the cache memory. Like the cache, the cache TAG comparator has an array of conventional static random access memory (SRAM) cells. A cache TAG comparator typically has two operating modes: write mode; and read/compare mode. When data is written into the cache memory, the higher order bits of the address of the data are stored in the TAG array. When in the read/compare mode, the cache TAG comparator compares a processor generated address to the TAG address. If the TAG address and the processor generated address are the same, a cache "hit" occurs, and a match signal of a predetermined logic state is provided by the cache TAG comparator, indicating that the requested data is located in the cache memory. If the processor generated address and the TAG address are not the same, a cache "miss" occurs, and a match signal of an opposite logic state is provided by the cache TAG comparator, indicating that the requested data is not located in the cache memory.
It is important for the match signal to be generated as quickly as possible after the cache TAG comparator receives the data to be compared. In some prior art cache TAG comparators, the read mode and the compare mode share the same data path, which results in increased gate delay before the match signal can the provided to the processor. Also, if redundancy is used to correct defects in the TAG array, the redundant path will also add delay to the time required to generate a match signal.